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Computer composition principle 5.2 instruction execution process


One 、 The concept of instruction cycle :

CPU The time taken to fetch and execute an instruction from main memory is called the instruction cycle . An instruction cycle contains several machine cycles ( Machine cycles are also called CPU cycle ); A machine cycle contains several clock cycles ( Clock cycle is also called beat or T Cycle or CPU Clock cycle , yes CPU The most basic unit of operation ). The number of machine cycles in each instruction cycle can be different , The number of clock cycles in each machine cycle can also be different . Different instructions may have different instruction cycles , Such as : The principle of computer organization 5.2 Instruction execution process


1. notes : The time required to analyze the instruction is short enough, so it belongs to the stage of fetching the instruction

2. notes : In general, after each instruction is executed, it will enter the interrupt cycle 3. notes : Interval period CPU Indirect addressing


Machine cycle can be divided into fixed length machine cycle and indefinite length machine cycle , Its essence is that the number of clock cycles contained in a machine cycle is different , Here's the picture , A square wave represents a clock cycle , Machine cycles of different lengths contain different numbers of waves ( The next picture red represents a clock cycle ).  The principle of computer organization 5.2 Instruction execution process
1.2 The four cycles involved in the above instructions :

Take the period : Take an instruction from main memory . Interval period : Convert a formal address into a valid address , That is, get the valid address of the operand . Execution cycle : Execute the operation corresponding to the instruction . Interrupt cycle : In the non off interrupt state , At the end of each instruction, an interrupt cycle is left to detect the interrupt signal .

Q: How to determine CPU In which cycle :

 The principle of computer organization 5.2 Instruction execution process A: Set four triggers , One... Is stored in each trigger 0 or 1,1 Indicates that it is in the current cycle ,0 Indicates that it is not in the current cycle , control unit CU In the control trigger is 0 still 1.

Two 、 The data flow direction of the instruction cycle :

2.1 Take the period

1).PC The next instruction storage address is stored in , So the PC Send the address saved in to MAR, Write it down as (PC)->MAR;2). control unit CU(Control Unit) Send control signals to the main memory through the control bus , The message is read (R) The signal , Write it down as 1->R;3).MAR The data stored in the main memory address is sent to... Via the data bus MDR, Write it down as M(MAR)->MDR;4).CU Send out control signals , Form the address of the next instruction , Write it down as (PC)+1->PC. The diagram of data flow is :

 The principle of computer organization 5.2 Instruction execution process
2.2 Interval period

1).IR The address code of the instruction in MAR, here MDR There is still something left in IR When the data is , Therefore, it can also be passed directly MAR Send in MDR, Write it down as Ad(IR)->MAR perhaps Ad(MDR)->MAR;2).CU Send a read message through the notification bus (R) The control signal is sent to the main memory , Write it down as 1->R;3).MAR The data stored in the main memory address is sent to... Via the data bus MDR, Write it down as M(MAR)->MDR;4). Enter a valid address into the address code field of the instruction , Spell out new instructions , Write it down as (MDR)->Ad(IR). This step can not be operated , Of some types only CPU. The diagram of data flow is : The principle of computer organization 5.2 Instruction execution process

2.3 Execution cycle

There are a variety of instructions for the execution cycle

2.4 Interrupt cycle

1).CU Control stack top address SP-1, Send the modified address to MAR, Write it down as (SP)-1->SP,(SP)->MAR, The essence is to store the process breakpoints in the storage unit of main memory ;2).CU Send a write control signal to the main memory through the control bus , Write it down as 1->W;3). The content of the breakpoint information is sent to MDR, Write it down as (PC)->MDR;4).CU The control sends the program entry address of the interrupt service to PC, Write it as a vector address ->PC. The diagram of data flow is :

 The principle of computer organization 5.2 Instruction execution process

1. notes :W and R They refer to write and read operations, respectively , Two interfaces are set in main memory W and R,W The on high level is 1 Write operation ,R Empathy .2. notes : similar M(MAR)->MDR This way of writing ,M(MAR) Meaning for MAR Content stored in .3. notes : The address period is marked in red , The previous article introduced that the instruction is only composed of operation code and address code , The address code part can store the address of the instruction or the address of other operands .4. notes : In fact, the top pointer of the stack register in the computer , From top to bottom, that is, from high to low , Therefore, the interrupt cycle has “CU Control stack top address SP-1” This operation , It means that the pointer at the top of the stack moves down one to point to the new position .


3、 ... and 、 Instruction execution scheme :

3.1 Single instruction cycle
 The principle of computer organization 5.2 Instruction execution process Serial execution between instructions , The execution cycle length of each instruction is the same . The length of the instruction cycle depends on the execution time of the longest instruction in the execution process .
3.2 Multiple instruction cycles

Unlike a single instruction cycle , In multiple instruction cycles, the execution cycle of each instruction can be different . Multi instruction cycle instructions are also executed serially .

3.3 Pipeline solution

When each instruction uses different hardware , Pipeline scheme can be adopted .

 The principle of computer organization 5.2 Instruction execution process

Leave a pit here for subsequent supplement ....

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