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[computer composition principle] Chapter 2 hardware structure of computer system

Textbook based 《 The principle of computer organization The first 3 edition 》 —— Tang shuofei

The system bus

The basic concept of bus

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Why use a bus

In the early days, when there were few external computer equipment, the original decentralized connection mode was mostly adopted , It is not easy to increase or decrease external equipment at any time . In order to better solve I/O The flexibility of the connection between the device and the host , The structure of the computer starts from Decentralized connection Develop into Bus connection .

Knowledge point :

1️⃣ A bus is an information transmission line connecting multiple components , yes Transmission medium shared by all components .

2️⃣ At some point , Only one part is allowed to send information to the bus , Multiple components can receive the same information from the bus at the same time . If there are multiple components in the system , Then they can only time-sharing Send information to the bus

Bus classification

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Characteristics and performance indexes of bus

Bus characteristics

1️⃣ mechanical properties : Some characteristics of bus in mechanical connection mode ( Size 、 shape 、 Number of pins 、 Arrange in order ……)

2️⃣ Electrical characteristics : The transmission direction and effective level range of the signal on each transmission line of the bus

3️⃣ features : The function of each transmission line in the bus ( Address 、 data 、 Control signals )

4️⃣ Time characteristics : Relationship between signal and timing

Performance index of bus

1️⃣ Bus width : Number of data lines (bit)

2️⃣ Bus bandwidth : Maximum bytes transferred per second (MBps)= Bus operating frequency × Bus width (bit/s)= Bus operating frequency ×( Bus width /8)(B/s)= Bus width / Bus cycle (bit/s) = ( Bus width /8)/ Bus cycle (B/s)

3️⃣ Clock synchronization / asynchronous : Whether the data on the bus is synchronized with the clock

4️⃣ Bus multiplexing : Address line And cable Multiplexing and time-sharing transmission on the line Address signal and Data signals , Can improve bus utilization

5️⃣ Number of signal lines : Address bus 、 data bus 、 Control bus The sum of the

6️⃣ Bus control mode : Sudden work 、 Automatic configuration 、 arbitration 、 Logic 、 Count

7️⃣ Other indicators : Load capacity 、 Supply voltage ……

8️⃣ Bus cycle : Time required for one bus operation ( Including the application stage 、 Addressing phase 、 Transmission phase and end phase ), It usually consists of several bus clock cycles .

9️⃣ The operating frequency of the bus : Frequency of various operations on the bus , Is the reciprocal of the bus cycle . If bus cycle =N Clock cycles , Then the operating frequency of the bus = clock frequency /N. Actually, it means transmitting data several times a second .

1️⃣0️⃣ Clock cycle of bus : That is, the clock cycle of the machine . The computer has a unified clock , To control all parts of the whole computer , The bus is also controlled by this clock .

1️⃣1️⃣ The clock frequency of the bus : That is, the clock frequency of the machine , Is the reciprocal of the clock cycle . If the clock cycle is T, Then the clock frequency is 1/T. It actually refers to how many clock cycles there are in a second .

Be careful :
1️⃣ Bus bandwidth refers to the maximum transmission rate that the bus itself can achieve .
2️⃣ When calculating the actual effective data transfer rate , Divide the amount of data actually transmitted by the time taken .

Bus standards

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Bus structure

Single bus structure

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Dual bus structure

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Three bus structure

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Bus control

Bus optimization control

Main equipment : A device that obtains control of the bus .
Slave device : The device accessed by the master device , It can only respond to various bus commands sent from the master device .

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Chain query

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Counter timing query

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Independent request mode

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Bus communication control

1️⃣ Purpose : Resolve the communication between the two parties Coordination problem

2️⃣ Bus transmission cycle

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Four ways of bus communication

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Synchronous communication mode

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Asynchronous communication

1️⃣ classification

2️⃣ Advantages and disadvantages

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3️⃣ Data transfer rate

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Semi synchronous communication mode

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Separate communication

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Memory

Memory classification

The hierarchy of storage

The relationship between the three main characteristics of memory

cache —— Main memory hierarchy and main memory —— Secondary storage level

1️⃣ cache —— The main memory level mainly solves CPU The problem of mismatch with the main memory speed

2️⃣ Main memory —— Auxiliary storage mainly solves the capacity problem of storage system

3️⃣ Main memory —— The secondary storage level develops to form a virtual storage system .

Main memory

summary

The basic composition of main memory

Main memory and CPU The connection of

1️⃣ Driver 、 The decoder and read-write circuit are in the memory chip

2️⃣ MAR and MDR stay CPU In chip

3️⃣ Chip and memory CPU The chip can be connected by bus

Allocation of storage unit addresses in main memory

Technical indicators of main memory

1️⃣ storage capacity : The total number of bits of binary code stored in main memory , storage capacity ( position )= Number of storage units * Storage word length , storage capacity ( byte )= Number of storage units * Storage word length / 8

2️⃣ Storage speed

  • Access time : Memory access time = Read time + Write time
  • Access cycle : Two consecutive independent memory operations ( Read or write ) The required Minimum interval time

3️⃣ Memory bandwidth : The amount of information accessed by the memory per unit time , Bits accessible per storage cycle ( byte ) Count / Storage cycle

Measures to improve memory bandwidth

  • Shorten storage cycle
  • Increase storage word length
  • Add storage

Introduction to semiconductor memory chip

Basic structure of semiconductor memory chip


1️⃣ Address line : One way input , The number of bits is related to the number of stored words

2️⃣ cable : Bidirectional , Digit and reading / The number of data bits written is related to

3️⃣ Control line

  • read / Write control line : Decide to read the chip / Write operations
  • Film selection line : Select memory chip

Decoding driving mode of semiconductor memory chip

Line selection

1️⃣ characteristic : A word selection line ( Wordline ), Directly select each member of a storage unit

2️⃣ Simple structure , Only suitable for memory chips with small capacity

To be legal again

1️⃣ characteristic : The selected unit is composed of X、Y The addresses in both directions determine

2️⃣ Suitable for memory chips with large capacity

Random access memory ( RAM )

static state RAM (SRAM)

Basic circuit

dynamic RAM ( DRAM )

Basic circuit

dynamic RAM Refresh

1️⃣ How often do I need to refresh : Refresh cycle is generally 2 ms

2️⃣ How many storage units are refreshed each time : Behavior unit , Refresh one row of storage units at a time
———— Why use row and column addresses : Reduce the number of strobes

3️⃣ How to refresh : Hardware support , Read out a line of information and write it again , Occupy 1 Individual reading / Write cycle

4️⃣ When to refresh :

dynamic RAM And static RAM Comparison

read-only memory (ROM)

Memory and CPU The connection of

Expansion of memory capacity

Bit expansion ( Increase storage word length )

The film selection line is the same , Assign data lines

Word extension ( Increase the number of stored words )

The data lines are the same , Set slice selection line

word 、 Bit simultaneous expansion

Both data line and film selection line should be reconsidered

Examples and problem solving steps

For the system program area ROM, For the user program area RAM

1️⃣ Write the corresponding binary address code

2️⃣ Determine the number and type of chips

From the title CPU cable 8 root , Then the number of memory bits should be expanded to 8 position . Then according to the memory chip given by the topic

Select a piece of... In the system program area 2 K * 8 Bit memory chip

Select two pieces in the user program area 1 K * 4 Bit memory chip

3️⃣ Assign address lines

4️⃣ Determine the chip selection signal

RAM He is an outsider , Shared selection line , Assign data lines

and ROM and RAM It is necessary to consider the setting of film selection line

Of the decoder Y4 The end can be used as ROM Chip selection port

Of the decoder Y5 End sum RAM Of A10 Address lines can be combined as RAM Film selection control

There is a default principle : Don't leave any address lines empty !!!

5️⃣ Connection diagram

6️⃣ Attention to details

ROM Be grounded

And the door have taken non , In other words, the input data are 0 when , Output is 1

RAM Address line assignment ,RAM To connect the read-write control line WR

At the enable end, only the input signal is G1 G2A G2B: 1 0 0 Work only when

The real question

The difference between this question and the previous one is RAM Word expansion, not bit expansion , So the data lines are the same , The film selection line shall be configured , use A12 As a division

Memory verification

Haiming code

The default is even parity , If the title requires odd check , Whether it's seeking Hamming code or error correction , Each operation ends with an XOR 1 .

Measures to improve the speed of memory access

  • High speed devices are used

  • Use hierarchy Cache - Main memory

  • Adjust the main memory structure

Single multiword system

General memory : Each row is a storage unit

Single multi word memory

Each storage unit stores m A word , Every word w position , The bus width is m A word . It can be read out in one access cycle m A word , That is to say m * w Bit instruction or data , Increase the main memory bandwidth to m times

shortcoming : Instructions and data must be stored continuously in main memory , Once a branch instruction is encountered , Or operands cannot be stored continuously , The effect of this method is not obvious

Multi body parallel system

  • High cross ( Sequential storage )

    • The storage unit of the memory bank is grouped by the high bit of the address , Storage units with the same high-order address belong to the same memory bank

    • CPU There is a high probability that you need to access the same bank continuously , Low efficiency

  • Low cross ( Cross storage )

    • The storage unit of the memory bank is grouped by the low order of the address , Storage units with the same low order address belong to the same memory bank

    • CPU Multiple banks can be accessed at the same time with a high probability , Efficient , Belong to Assembly line

    • Without changing the access cycle of each module , Increase memory bandwidth

    • Can work in parallel , If the bus width is mw when , The length of... Can be taken out at the same time mw The data of . Equivalent to high-order cross storage m Multiple banks work in parallel

The concept of pipeline

Example

Equipped with 4 A four body memory structure composed of four modules , The storage word length of each body is 32 position , The storage period is 200 ns. Assume that the data bus width is 32 position , The bus transmission cycle is 50 ns, Try to find the memory bandwidth of sequential storage and cross storage .

Explain : Sequential storage and cross storage are continuously read out 4 The amount of information in a word is 32 * 4 = 128 position .

Sequential memory continuous readout 4 The time of a word is 200 ns * 4 = 800 ns

Cross store its continuous readout 4 The time of a word is 200 ns + 50 ns * (4 - 1) = 350 ns

The bandwidth of sequential memory is 128 b / 800 ns = 16 * 10 ^ 7 bps

The bandwidth of cross memory is 128 b / 350 ns = 37 * 10 ^ 7 bps

Cache memory

summary

Locality principle

CPU And main memory (DRAM) There is a difference in the speed of , for fear of CPU There may be “ Empty wait ” The phenomenon

Performance analysis

1️⃣ hit :
1. Main memory block Transfer in cache
2. Main memory block and cache block establish The corresponding relationship
3. use Mark the record That has established a corresponding relationship with a cache block Main memory block number

2️⃣ Not hit :
1. Main memory block Not transferred in cache
2. Main memory block and cache block Not established Corresponding relation

3️⃣ Cache shooting :
1.CPU The information you want to access is in Cache Medium ratio
2. shooting And Cache Of Capacity And Block length of

4️⃣ The efficiency of the main memory system
1. efficiency e And shooting of

Example

Cache Basic structure

Cache Read and write operations

read

Write

Cache Improvement

1️⃣ Single cache and L2 cache

2️⃣ Unified cache and discrete cache

Cache – Address mapping of main memory

Direct mapping

1️⃣ Each cache block i It can correspond to several main memory blocks
2️⃣ Each main memory block j Can only correspond to one cache block
3️⃣ i = j mod C (C yes Cache Total number of blocks )

All associative mapping

In main memory Any block Can be mapped to... In the cache Any block

Group associative mapping

A main memory block j Press mold Q Mapping to cache Of the i Any block in the group

n The road groups are connected :Cache n A group of blocks , namely Q = n

1️⃣ When n = 1 when ,Cache Divide into 1 Group , Equivalent to fully associative mapping

2️⃣ When n = Cache When the number of block lines ,Cache Each block of is a group . Equivalent to direct mapping

Summary of three mapping methods

Replacement algorithm

Example 1

FIFO: Within each group , It's just a small queue , Move the whole group up one unit , Put the new element below , Pop up the top element

LRU: In each group , Put the least commonly used on the top , Just used ( hit ) Put it at the bottom ; New elements are encountered and the group is full , Then the whole group moves up one unit , Put the new element at the bottom , Pop up the top element

Example 2

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